The present invention is directed to a multi-layer integrated circuit assembly for use in interfacing a planar array of input elements to external electronics.
The present invention finds application in relation to infrared detection circuits and, in particular, to large arrays of closely spaced infrared detector elements. Output signals from such elements must be separately received and processed in a reliable manner by supporting electronics. Though a certain amount of processing is preferably performed at or adjacent the focal plane, space and weight constraints typically limit the amount of such on focal plane processing that may be effected.
In order to address the connectivity and processing demands of electrically interfacing large arrays of closely spaced detectors a variety of techniques have been developed. Such prior techniques include the construction of various types of modules designed to support conductive patterns as well as a limited number of integrated circuits. One such module is disclosed in. U.S. Pat. No. 4,304,624 to CARSON, ET AL. The structure disclosed in that reference incorporates a base layer for supporting a plurality of integrated circuits and a plurality of adjacent layers formed to have apertures therein. In that construction distinct metalization patterns are formed on each of the layers, leading from edge portions of the layers to the apertures. The metalization patterns are then connected to dedicated integrated circuits by means of wire bonds and/or conductive vias vertically extending through the apertures formed in the stacked layers.
Though such a construction satisfies the connectivity and processing requirements of interfacing a closely spaced array of detector elements, leads and bonding pads require a large amount of layer area and a large number of bonding operations are needed. This method of connecting integrated circuits to the layers contributes to expense and potential reliability problems in the module.
In an alternate prior construction the insulating layers are eliminated and the integrated circuits are directly stacked. Such an approach is illustrated in U.S. Pat. No. 4,703,170 to SCHMITZ, assigned to the common assignee. Though this approach may be useful to eliminate the need to vertically communicate signals within the module, it requires that conductive patterns be formed directly on the integrated circuit substrate. That substrate may be formed of material such as bulk silicon or saphire depending upon performance requirements. The formation of conductive pads on vertical edges of the substrate may also be a tedious process in such a construction. Moreover, the wafer fabrication yield may be substantially reduced as the chip area is expanded to support the connectivity patterns.
Accordingly, it is desirable to develop a construction which avoids the vertical connection problems within a module without supporting the metalization patterns directly on the integrated circuit wafer. Moreover, it is desirable to provide a technique for forming such a module wherein each layer is of substantially the same construction and wherein wafer fabrication yield remains high. The present invention addresses these and other objects and disadvantages heretofore associated with the construction of contemporary multi-layer integrated circuit modules.